1. Field of the Invention
The present invention relates to an apparatus for correcting waveform distortion. In particular, the invention relates to an apparatus for correcting time distortion in a received signal which is modulated (for example by Bi-Phase-Mark modulation) and thereafter transmitted.
2. Background of the Invention
The Electronic Industries Association of Japan, EIAJ CP-340, has published an interface for Serial Data Transmission and Self Synchronizing Transmission for mutual communication among digital audio equipment. In the format for this digital audio interface, the method of Bi-Phase-Mark is an adopted channel coding method for modulation.
The coding under this Bi-Phase-Modulation is shown in FIG. 5. Clock pulses for modulation (at two times the bit rate) are illustrated in FIG. 5A. Source data represented by Non Return Zero (NRZ) coding are illustrated in FIG. 5B. The source data modulated by the B-Phase-Mark coding is illustrated in FIG. 5C.
When we define one interval of the modulation clock as T (which equals one half of a bit clock period), the Bi-Phase-Mark coding is a modulation method in which `1` and `0,` of the source data are respectively represented by a signal with an interval (1T) of inversion time from "1" to "0" and another interval (2T) of inversion time from "1" to "0" as illustrated in FIG. 5. As shown in FIG. 5C, a `1` in the source data is represented by a signal which turns from "1" to "0" with an inversion time (the time between state inversions) being equal to an interval (1T) and `0` in the source data is represented by another signal which turns from "1" to "0" with an inversion time of (2T).
This Bi-Phase-Mark method is a method of modulation in which an accumulated value of time interval represented by a signal "1" becomes equal to another accumulated value of time interval represented by another signal "0". Therefore, the Direct Current (DC) component in the transmitting line can be minimized. In addition, it is a method of modulation in which clock can be easily retrieved from the transmitted data signals.
The signal format of this standard for a digital audio interface is shown in FIG. 7. In this example, the digital audio data are divided into two stereo channels, and blocks of 192 frames from a frame #0 to #191. Each frame includes two subframes. In this two channel case, a channel #1 (for example as a left channel) is assigned as a subframe at the first half of one frame and a channel #2 (for example as a right channel) is assigned as a subframe at the second half of the frame. A subframe includes 32 bits (which corresponds to 64 modulation clocks). A four bit preamble of added data is inserted at a header of each subframe. This preamble can be utilized for synchronizing and identifying a subframe and a block. A special pattern is adopted as this preamble which does not appear in the previously mentioned data of Bi-Phase-Mark codings.
To distinguish a subframe at the first half of a frame from another at the second half, each preamble is different with respect to each other. Also, a special preamble of the first subframe at the beginning of a block is adopted to distinguish it from those for other subframes. Therefore, three different kind of synchronizing patterns, referred to as B, M and W, are provided. A typical example of these three patterns for the preamble B, M or W is illustrated in FIG. 6. As shown, two different patterns are prepared for each preamble B, M or W so that one of them can be selected depending on whether the previous symbol data as the Bi-Phase-Mark coding is "0" or "1". The polarity of signal is the only difference between these two patterns, therefore, they are basically the same signal.
As shown in FIG. 7, the preamble B is inserted at a header portion of the first subframe at the beginning of a block so that the block can be identified and synchronized. The preamble M is inserted at every header of subframes at the first half of each frame, except for the first subframe at the beginning of a block. The preamble W is inserted at every header of subframes at the second half of each frame. These preambles M and W can be utilized for identifying and synchronizing subframes. As understood by FIG. 6, considering a time interval needed for polarity conversion in these preambles B, M and W, the time interval for the first polarity of three of them is 3T, which doesn't appear as any of the Bi-Phase-Mark data.
In a conventional operation of receiving signals modulated by the above mentioned Bi-Phase-Mark, a modulated clock component and a word synchronizing component of data (3T component of preamble) is retrieved from the receiving modulated signal. Using these components as references with a Phase Lock Looped (PLL) circuit, modulation clocks and bit clocks can be generated for data. By these clock, extraction of modulated signals and demodulation of data can be performed.
FIG. 8 shows a block diagram as a example of the conventional data receiving circuit. A modulated signal under the Bi-Phase-Mark from a transmitter 1, is transmitted through a transmission line such as an optical cable 2 and then received by a receiver 3. The process of passing through the transmission line smoothes the waveform of the received data at the receiver 3 to approximate a sine wave. Therefore, the wave should be shaped to a square wave. One of the method of this wave shaping is performed by considering a DC level of the retrieved signal as a threshold value and comparing this threshold value of the received data.
The output signal from the receiver 3 is supplied to a clock component extractor 6 where the clock component can be extracted from the signal. The extracted clock component is then supplied to a Phase Lock Looped (PLL) circuit 10. The PLL circuit 10 includes a Voltage Controlled Oscillator (VCO) 11. An output from the VCO 11 is supplied to a counter circuit 12 working as a variable frequency divider. Plural signals with different frequencies can be obtained as output of the counter circuit 12. Among them, a signal having the frequency corresponding to the modulated clock is provided back to the phase comparator 13 to be compared with the clock component derived from the clock component extractor 6. An error output by the comparison output of the phase comparator 13, which represents a phase difference, is then supplied to the VCO 11 through a Low Pass Filter (LPF) 14. The oscillating output signal of this VCO 11 is therefore controlled so as to synchronize with the output signal of the cock component extractor 6. As the result, signals with different frequencies but synchronized with the clock component of the received signal can be obtained out of the counter 12. The signal out of the receiver 3 is also supplied to a signal extractor 4. The signal extractor 4 extracts signals "1" and "0" at timings synchronized with a clock received from the counter circuit 12 of the PLL circuit. An output signal from the signal extractor 4 is supplied to a decoder 5. The decoder 5 makes the Bi-Phase-Mark codings demodulated to the original NRZ data, based on a clock for decoding received also from the counter circuit 12.
As the DC level of the Bi-Phase Mark codings approaches zero, a threshold value for wave shaping at the receiver 3 is also set to zero. However, the output of receiver 3 sometimes includes time distortion. For example, once a DC offset occurs at a transmitting line or a receiving element, or the threshold value includes DC offset, the relative levels between the threshold value and the received signal vary. Therefore, the interval of signal to be "1" or "0" cannot be properly modulated. When this occurs, distortion may be generated.
As shown in FIG. 9A, when a threshold value is kept at th1, the time interval (time period needed for polarity inversion) of signals "1" or "0" can properly appear as show in FIG. 9B. However, if the threshold value deviates to th2, the interval of signals "1" and "0" may include time distortion as shown in FIG. 9C. If we still use the bit clock out of the PLL circuit 10 in FIG. 8 to extract signals "1" and "0" at the signal extractor 4 and the above mentioned time distortion, the timing between the clock and the signals of "1" and "0" would become different from each other. The erroneous extraction of signal can occur as mentioned above. To avoid this erroneous operation, it is better to remove the time distortion from the signal from the receiver 3 and then provide the signal extractor 4 with a received output signal. For that purpose, a method has been developed in which the square wave obtained through a wave shaping is converted to a triangle wave. The triangle wave is then supplied to a low pass filter so as to detect its DC level by which the threshold value of wave shaping may be controlled. However, in this method, since this is an analog control, adjustment is troublesome and signal to noise (S/N) ratio becomes worse resulting in a limited correction. Furthermore, as the whole signal out of the receiver may vary, the phase of the synchronizing pattern in the preamble may also deviate, further degrading the correction.